Browsing French translation

3018 of 4365 results
3018.
RISC-V options:
-m32 assemble RV32 code
-m64 assemble RV64 code (default)
-fpic generate position-independent code
-fno-pic don't generate position-independent code (default)
-msoft-float don't use F registers for floating-point values
-mhard-float use F registers for floating-point values (default)
-mno-rvc disable the C extension for compressed instructions (default)
-mrvc enable the C extension for compressed instructions
-march=ISA set the RISC-V architecture, RV64IMAFD by default
There are line breaks here. Each one represents a line break. Start a new line in the equivalent position in the translation.
There are leading/trailing spaces here. Each one represents a space character. Enter a space in the equivalent position in the translation.
(no translation yet)
Located in config/tc-riscv.c:2448
3018 of 4365 results

This translation is managed by Ubuntu French Translators, assigned by Ubuntu Translators.

You are not logged in. Please log in to work on translations.